Features:

	VHDL design optimized for FPGAs; works seamlessly with on-chip 32-bit CPUs, like for example Altera NIOSII
	Wire speed, full duplex 100Mbit/s operation
	2,4, and 8 x MII/RMII interfaces
	Intelligent packet forwarding (address learning)
	IEEE1588 support
	Low port-to-port delay: 3 us
	Error CRC checking and generation
	Linux device driver available
	Starter kit with CycloneIII evaluation board

For more information refer to the documents below
or contact Peter Jamitzky: peter.jamitzky@adescom.com