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VHDL design optimized for FPGAs; works seamlessly with on-chip 32-bit CPUs, like for example Altera NIOSII |
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DPV0 services fully implemented in hardware |
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Officially certified for compatibility with Profibus standard IEC 61158 |
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Compatible to Siemens DPC31 on functional and register levels |
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Up to 12 Mbits/s transmission rates |
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Gate complexity: 6,100LEs and 8KB internal RAM on Altera Cyclone EP1C12 device |
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Software stack available |
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Free evaluation versions (contact Adescom) |
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Starter kit with CycloneII evaluation board |
