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Committed to continuously improve price, performance, and power consumption of embedded systems, ADESCOM has developed a TCP/IP engine in hardware, code-named IPAC, which off-loads performance intensive Internet protocols from processor sub-systems and allows to better optimize embedded systems. This leads to a higher application performance, reduced clock frequencies and power consumption, and allows for use of 8/16 bit processor architectures - even in systems requiring high communication bandwidth.
Features:
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Sustained 100Mb/s and 1Gb/s bandwidth |
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Complete TCP/IP stack solution for IPv4 in VHDL: TCP. UDP, ICMP, ARP, DHCP, DNS, multicast |
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Up to 64k connetcions |
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Automatic data buffer management |
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AES enryption option |
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Integrated Ethernet MAC |
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18,000 LEs complexity (Altera, Cyclone III device) |
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Evaluation kit available |
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